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Литература: Программирование и ремонт Импульсные блоки питания Неисправности и замена Радиоэлектронная аппаратура Микросхема в ТА Рубрикатор ТА Кабельные линии Обмотки и изоляция Радиоаппаратура Гибкие диски часть 2 часть 3 часть 4 часть 5 Ремонт компьютера часть 2 Аналитика: Монтаж Справочник Электроника Мощные высокочастотные транзисторы 200 микросхем Полупроводники ч.1 Часть 2 Алгоритмические проблемы 500 микросхем 500 микросхем Сортировка и поиск Монады Передача сигнала Электроника Прием сигнала Телевидиние Проектирование Эвм Оптимизация Автомобильная электроника Поляковтрансиверы Форт Тензодатчик Силовые полевые транзисторы Распределение частот Резисторные и термопарные Оберон Открытые системы шифрования Удк
[2]
CPU Mstr Fast Interface216
CPU Mstr Post-WR Buffer217
CPU Mstr Post-WR Burst Mode217
CPU Multiple Read Prefetch134
CPU Multiple Reads133
CPU Operating Speed136
CPU Pipeline Function106
CPU Priority215
CPU Ratio136
CPU Read Multiple Prefetch134
CPU Read Prefetch134
CPU Serial Number71
CPU Sleep Pin Enable335
CPU Speed137
CPU Temperature360
CPU to DRAM Page Mode197
CPU to PCI Buffer116
CPU to PCI Burst Memory Write113
CPU to PCI Burst Write114
CPU to PCI Byte Merge111
CPU to PCi POST/BURST115
CPU to PC Read Burst114
CPU Warning Temperature360
CPU/PCI Burst Mem. Write114
CPU/PCI Post Mem. Write116
CPU/PCI Post Write Delay117
CPUFAN Off in Suspend359
CPUID Instruction63
CPU-to-AGP 1WS Burst Write319
CPU-to-AGP Dynamic Bursting319
CPU-to-AGP Post Writes319
CPU-to-DRAM 8 QW FIFO119
CPU-to-DRAM Buffer Timing119
CPU-to-DRAM Byte Merging119
CPU-to-DRAM FIFO Cleaning119
CPU-to-DRAM Posting119
CPU-to-IDE Posting115
CPU-to-PCI 6 DW FIFO112
CPU-to-PCI Bridge Retry113
CPU-to-PCI Bridge Retry113
CPU-to-PCI Bursting114
CPU-to-PCI FIFO Cleaning115
CPU-to-PCI IDE Posting115
CPU-to-PCI Post Writes116
CPU-to-PCI Posting116
CPU-TO-PCI Prefetch211
CPU-to-PCI Read Buffer115
CPU-to-PCI Read-Line133
CPU-to-PCI Write Buffer116
CPU-to-PCI Write Bursting114
CPU-to-PCI Write Delay116
CPU-to-PCI Write Latency116
CPU-to-PCI Write Post116
CPU-to-PCI Write Posting116
CPU-to-PCI Write Waits116
Critical Events in Log371
Cyrix 6x86 / MII CPU ID64
Cyrix M2 ADS# delay132
D000,16K Shadow150
D0000-D3FFF Shadow149
D400,16K Shadow150
D4000-D7FFF Shadow149
D800,16K Shadow150
D8000-DBFFF Shadow149
Data Integrity (PAR/ECC)141
Data Integrity (PAR/ECC)142
Data Read 0 WS220
Data Write 0 WS220
Daylight Saving64
DC00,16K Shadow150
DC000-DFFFF Shadow149
Decoupled Refresh185
Decoupled Refresh Option185
Default Latency Timer Value226
Default Latency Timer: [Yes]226
Default Primary Video236
Delay For HDD (Secs)65
Delay for SCSI/HDD (Secs)65
Delay IDE Initial64
Delay on Option ROMs70
Delayed Transaction117
Delayed Transaction Optimization117
Delayed Transaction Timer117
Deturbo Mode81
Dirty pin selection179
Diskette A:/B:66
Diskette Controller237
Diskette Write283
Diskette Write Protect283
Display Activity348
Display Cache Window Size209
Display Mode at Add-On ROM Init70
DMA Ch N TypeF Transfers270
DMA Channel294
DMA Channel n268
DMA Clock267
DMA Clock Selection267
DMA Clock Speed267
DMA Line Buffer Mode268
DMA n Assigned to268
DMA n Used By ISA269
DMA Wait States269
DMA/ISA Master Before PCI215
DMA-n assigned to250
DMA-n Type268
DPMS Supported337
DRAM Auto Configuration195
DRAM Burst at 4 Refresh186
DRAM CAS Timing Delay196
DRAM Clock198
DRAM Data Integrity Mode141
DRAM ECC/PARITY SELECT141
DRAM ECC/PARITY Select142
DRAM Enhanced Paging198
DRAM Idle Timer200
DRAM Integrity Mode141
Список опций | |
DRAM Interleave Mode | |
DRAM Page Closing Policv | |
DRAM Page Idle Timer | |
DRAM Page Mode | |
DRAM Page Open Policy | |
DRAM Paging | |
DRAM Paging Mode | |
DRAM Posted Write | |
DRAM Posted Write Buffer | |
DRAM RAS Only Refresh | |
DRAM RAS to CAS Delay | |
DRAM RAS# Precharge Period | |
DRAM RAS# Precharge Time | |
DRAM Read-Around-Write | |
DRAM Refresh Cycle Time | |
DRAM Refresh Method | |
DRAM Refresh Period | |
DRAM Refresh Queing | |
DRAM Refresh Queue | |
DRAM Refresh Queue Depth | |
DRAM Refresh Rate | |
DRAM Refresh Stagger By | |
DRAM Refresh Type | |
DRAM Slow Refresh | |
DRAM Speed | |
DRAM Speed Selection | |
DRAM Write CAS Width | |
Drive A | |
Drive B |
Drive NA before BRDY127
Duplex Mode290
Duplex Select290
Dynamic Bursting114
Dynamic PCI Bursting114
E0000 ROM belongs to ATBUS152
E8000 - EFFFF Shadow149
E8000 32K Accessible152
Early PCI Bus Request110
ECC Configuration142
ECC Control141
ECC CPU Checking141
ECC Memory Checking141
ECP DMA Select294
ECP Mode Use DMA294
Edge/Level Select260
EDO DRAM Speed (ns)200
EDO DRAM Speed Selection200
EDO MD Timing124
EDO RAS Precharge186
EDO RAS Precharge Timing186
EDO RAS to CAS Delay205
EDO RAS# Precharge Time186
EDO/SDRAM RAS# Pulse Width204
Embedded SCSI BIOS326
EMP Access Mode366
EMP Direct Connect/Modem Mode367
EMP Escape Sequence367
EMP Hangup Line Sequence367